Curriculum vitae

Founding Engineer, DSP

Spacetech startup

Signal-processing for spaceborne hardware — architecture through implementation.

Analog Design Engineer

Texas Instruments India · Bengaluru

• Designed the transmitter for an ISO- and EMC-compliant CAN protocol transceiver for automotive use (Jul 2023 – Dec 2024).
• Designed the IO transmitter interface for an Ethernet standard (Dec 2024 – Mar 2025).
• Guided silicon measurements and characterization for the transceiver (Mar 2025 – ).

B.Tech in Electrical Engineering with M.Tech in Microelectronics

Indian Institute of Technology Bombay · CGPA 9.44 / 10.0

• Minor degree in Computer Science & Engineering.
• Dual-degree thesis on the NEGF formalism under Prof. Bhaskaran Muralidharan.

Small-signal NEGF for impedance characterization of nanoscale devices

Dual-degree thesis · Guide: Prof. Bhaskaran Muralidharan, EE, IIT Bombay

• Surveyed the physics of NEGF, topological interconnects, and scattering formalism.
• Developed code replicating an AC-NEGF setup for carbon nanotubes coupled with a Poisson solver.

Weak-value measurements for spin-traversal time

IIT Bombay

Literature survey on weak values, quantum metrology, and the spin-traversal-time measurement setup.

Analysis & modelling of periodic gratings

AIMS Lab, IIT Bombay

• Simplified an analytical model for reflectivity and waveguide modes of 1-D gratings to explore III–V high-contrast-grating modulators.
• Wrote MATLAB code reaching ~25% of the runtime of an RCWA-based reference.

System-level design of FFE filter, SerDes & phase detector

EE800: High-Speed Interconnects

Designed and characterized a serializer–deserializer and phase detector in Verilog-A (Cadence); trained an FFE filter for receiver-side pulse-shaping over a lossy transmission line.

Neural networks on FPGA for image classification

EE705: VLSI Design Lab

Trained a CNN on CIFAR-10 in TensorFlow and implemented synthesizable CNN layers in VHDL.

Wavelet-based ECG delineator & compression

EE338: Digital Signal Processing

Used quadratic-spline wavelet filter banks and the à-trous algorithm for ECG delineation, and SVD for compression — up to 98% R-peak detection on PhysioNet signals.

• All-India Rank 320 in JEE Advanced (≈ 0.15 million candidates).
• All-India Rank 680 in JEE Mains (≈ 1 million candidates).
• All-India Rank 100 in the KVPY fellowship exam, IISc Bengaluru.

MATLAB · C · C++ · Cadence · NgSpice · Magic · VHDL · Verilog · Verilog-A · Git · AutoCAD · Eagle · Altium

Python · TensorFlow · Keras · Tableau

• Volunteered at St. Broseph's Foundation, Bengaluru — automating and digitizing RTI request handling.
• Completed a two-semester course in Chinese (中文) at IIT Bombay.