shlokvaibhav.github.io

Sapere Aude! (Or Dare to Think!)

Hi, I’m Shlok Vaibhav, a chip-designer on Ethernet-SerDes product line at Texas Instruments India. I am also an open-source contributor to PhysLean. I did my undergrad and masters at Indian Institute of Technology, Bombay. I am interested in time-domain simulation of nanoelectronics structures using Non-Equilibrium Green’s Function approach.

I am also interested in Sinology and Enlightement Era.